Recently, devices such as cellular phones, personal digital assistances and DVC (digital video camera) have been significantly improved in their performance, getting smaller and lighter, and for semiconductor package improvement of performance, down sizing and lightening have been strongly required. There have been, therefore, attempts to mount a plurality of semiconductor elements having different functions or a plurality of semiconductor elements having the same function in one package for improving performance of a semiconductor package, or to make the size of a semiconductor package closer to the size of an element as much as possible for size- and weight-reduction. Thus, semiconductor elements have been much thinner and a distance of a wire-bond pad between a semiconductor element and a support such as a metal or organic substrate has been shorter and shorter.
In a die attach step in a conventional assembling process for a semiconductor, a liquid die attach material is applied on a support and a semiconductor element is mounted on it at room temperature and then cured by heating for adhesion of the semiconductor element to the support, but there have emerged potential problems such as contamination of a die attach material to the surface of a semiconductor element or a wire-bond pad and contamination due to bleeding of a die attach material (a phenomenon that only a liquid ingredient in a die attach material moves via capillary phenomenon).
Thus, alternative processes have been employed, including attaching a film die attach material instead of a liquid die attach material to a support, on which a semiconductor element is mounted under heating; attaching a semiconductor wafer with a film die attach material on the back surface to a dicing sheet, which is cut into pieces to give a semiconductor element with a die attach material, which is then mounted on a support under heating; and attaching a semiconductor wafer to a die attach film acting as a dicing sheet, which is then cut into pieces to give a semiconductor element with a die attach material, which is then mounted on a support under heating (for example, see Patent References 1 and 2).
Meanwhile, not only a semiconductor element but also a support have been thinner as a trend of multi-layered stacking of semiconductor element and thinning of semiconductor package. The use of a thin support leads to more prominent warpage of a package due to a difference in a coefficient of thermal expansion among composition of semiconductor package. Furthermore, an insulating film with a low dielectric constant is used as an interlayer insulating film for reducing transmission delay due to reduction in a signal propagation rate caused by a parasitic capacitance between interconnections in order to provide a higher-speed semiconductor device, but generally, an insulating film with a low dielectric constant is brittle and warpage of a semiconductor element may lead to crack or delamination of the insulating layer.
Since warpage of a semiconductor package or semiconductor element is caused by a difference in a coefficient of thermal expansion between constituting members, it is desired to mount a semiconductor element at a reduced temperature when using a film die attach material.
It is, therefore, necessary to use a thermoplastic component with a low glass transition temperature or to increase components with a low molecular weight as an ingredient of film die attach material for lowering a temperature during mounting a semiconductor element, but it leads to occurrence of tackiness (stickiness) even at a temperature near an ambient temperature.
Stickiness at a temperature near an ambient temperature may often cause deterioration in pick-up properties in the step of peeling a semiconductor element from a dicing sheet and adhesion of a semiconductor element picked up to a stage in the step of temporarily placing it on a different stage (for example, see Patent References 3 to 5).
There have been several attempts to use a material which is not tacky at an ambient temperature, as a encapsulant for a wafer level chip size package (for example, Patent References 6 to 8). In these inventions, a resin composition is applied to a wafer with a bump such as solder and made non-tacky by heating before being cut into pieces, but it must be subjected to bonding at a temperature of a melting point of a solder or higher because encapsulating and solder bonding are simultaneously conducted in a subsequent step.
As described above, there are no resin compositions meeting the requirement that they can be mounted at a low temperature while not being sticky at an ambient temperature.    Patent Reference 1: Japanese published unexamined application No. 2002-294177;    Patent Reference 2: Japanese published unexamined application No. 2003-347321;    Patent Reference 3: Japanese published unexamined application No. 1994-132327;    Patent Reference 4: Japanese published unexamined application No. 1995-201897;    Patent Reference 5: Japanese published unexamined application No. 2000-252303;    Patent Reference 6: Japanese published unexamined application No. 2000-174044;    Patent Reference 7: Japanese published unexamined application No. 2001-93940;    Patent Reference 8: Japanese published unexamined application No. 2003-212964.